This invention relates to bipolar multiplexers, and more specifically to an improved select buffer circuit for use in combination with such bipolar multiplexers.
Various types of improved logic gate and buffer circuits, including several having means for discharging an output transistor, are shown in the prior art. Some typical examples of such circuits are shown in U.S. Pat. Nos. 4,321,490; 4,132,906; 4,131,808; RE. 27804; and Japanese Patent Publication No. 58-19032. In U.S. Pat. No. 4,703,202, a problem similar to that addressed by the present invention is solved in a different manner.
While the prior art is directed to various ways of generally improving the performance of logic gate and buffer circuits, it does not recognize or address the particular problem solved by the present invention. This problem, which is described in further detail below, concerns the presence of a so-called "output glitch", an unwanted transitory shift in output signal level at a time when the output voltage level should remain substantially constant. This "output glitch", which is caused by a timing delay within the select buffer circuit of the bipolar multiplexer, constitutes a substantial performance drawback in conventional bipolar TTL multiplexers.
Accordingly, it would be desirable to have a select buffer circuit suitable for use in bipolar multiplexers which is capable of eliminating the multiplexer "output glitch". Ideally, such an improved select buffer circuit would not deteriorate the switching performance or increase the power consumption of the bipolar multiplexer. Additionally, the improved circuit should be relatively simple and easy to implement.